1. Field of the Invention
The invention relates generally to large block size error correction encoding and decoding systems and, more particularly, to large block size low density parity check code systems.
2. Background Information
One way to improve the performance of error correcting codes is to use larger block sizes. A known prior system described in U.S. Pat. No. 6,275,965 to Cox, et al. uses Reed-Solomon error correcting codes (“ECC's”) and two levels of encoding to handle a larger block size. The Cox system segments the d data bytes into multiple-bytes segments and simultaneously encodes the segments and certain combinations thereof using two ECCs, to produce redundancy information that corresponds to both the segments and the block. The Cox system then produces an encoded block, which consists of an interleave of the data and the redundancy information.
The Cox system decodes the encoded block by simultaneously de-interleaving and manipulating the data symbols of the block in accordance with the two ECC's, to generate associated redundancy information, that is, the system generates both segment and block redundancy information. The Cox system then uses the generated segment and block redundancy information and the segment and block redundancy information that is included in the encoded block to generate error syndromes that correspond, respectively, to the individual segments and to the block. The system uses both the segment and the block error syndromes to detect and, if possible, correct errors in the data. The Cox system thus manipulates the entire block to generate the redundancy information that is required for error correction.
While the two-level system works well with Reed-Solomon ECC's, the ECCs of interest are low density parity check (“LDPC”) codes, which are a different class of codes that generally have a better performance than the Reed Solomon ECCs. The LDPC ECCs use “soft” decision information. The soft information for a single bit of the encoded block consists of a sign, or bit, value and a plurality of bits of reliability information. The LDPC block decoding operations involve iteratively updating the sign value and the reliability information that correspond to the bits of the encoded block until either the result converges or a predetermined number of iterations are performed. Accordingly, the sign and the reliability information for the entire block must be retained in buffers for the decoding of the block, and the buffers must be many times as large, for example, 4 or 5 times as large, as the number of bits in the block. The large buffers add both complexity and cost to the system.
One solution is to encode and decode the block data both as sub-blocks of data using an LDPC code and in its entirety using a Reed Solomon ECC. The problem with this solution, however, is that the sub-block and block ECC's are of different classes, which means that different decoding hardware is required for the block decoding and for the sub-block decoding. Thus, this solution essentially trades one type of hardware complexity, i.e., large buffers, for another, and results in little, if any, savings in gate count and/or associated cost. Further, the better performance LDPC code is used only for the shorter sub-blocks, and thus, the benefits of using the LDPC code are not provided over the larger block.
Accordingly, what is needed is a system and method for LDPC decoding that takes advantage of block level LDPC encoding but does not require the buffering of the soft information for the entire block.